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authorEric Christopher <echristo@apple.com>2012-04-03 01:16:32 +0000
committerEric Christopher <echristo@apple.com>2012-04-03 01:16:32 +0000
commit0ea6164a7ff685f64ddfe3ec983a2b052ea91afb (patch)
treedc2014a8d44c550a0ed37c8fb6fb082d771836f7
parentea32047660159811a4c14d008a4b7e3807a705d6 (diff)
Add more constraint registers for mips.
Patch by Jack Carter. Testcase cleanup by me. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@153921 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Basic/Targets.cpp3
-rw-r--r--test/CodeGen/mips-constraint-regs.c44
2 files changed, 47 insertions, 0 deletions
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index eacdf5e3e1..1fcef3392f 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -3522,6 +3522,9 @@ public:
case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backwards compatibility only.
case 'f': // floating-point registers.
+ case 'c': // $25 for indirect jumps
+ case 'l': // lo register
+ case 'x': // hilo register pair
Info.setAllowsRegister();
return true;
}
diff --git a/test/CodeGen/mips-constraint-regs.c b/test/CodeGen/mips-constraint-regs.c
new file mode 100644
index 0000000000..075be058dc
--- /dev/null
+++ b/test/CodeGen/mips-constraint-regs.c
@@ -0,0 +1,44 @@
+// RUN: %clang -target mipsel-unknown-linux -ccc-clang-archs mipsel -S -o - -emit-llvm %s
+
+// This checks that the frontend will accept inline asm constraints
+// c', 'l' and 'x'. Semantic checking will happen in the
+// llvm backend. Any bad constraint letters will cause the frontend to
+// error out.
+
+int main()
+{
+ // 'c': 16 bit address register for Mips16, GPR for all others
+ // I am using 'c' to constrain both the target and one of the source
+ // registers. We are looking for syntactical correctness.
+ int __s, __v = 17;
+ int __t;
+ __asm__ __volatile__(
+ "addi %0,%1,%2 \n\t\t"
+ : "=c" (__t)
+ : "c" (__s), "I" (__v));
+
+ // 'l': lo register
+ // We are making it clear that destination register is lo with the
+ // use of the 'l' constraint ("=l").
+ int i_temp = 44;
+ int i_result;
+ __asm__ __volatile__(
+ "mtlo %1 \n\t\t"
+ : "=l" (i_result)
+ : "r" (i_temp)
+ : "lo");
+
+ // 'x': Combined lo/hi registers
+ // We are specifying that destination registers are the hi/lo pair with the
+ // use of the 'x' constraint ("=x").
+ int i_hi = 3;
+ int i_lo = 2;
+ long long ll_result = 0;
+ __asm__ __volatile__(
+ "mthi %1 \n\t\t"
+ "mtlo %2 \n\t\t"
+ : "=x" (ll_result)
+ : "r" (i_hi), "r" (i_lo)
+ : );
+ return 0;
+}